I can't imagine that leaves too many CPU cycles for anything other than bit banging ... is there an actual use case for this, or just a fun project ?
That's the power of the Pico - the bit-banging happens in the PIOs, not the main cores. So idling takes no CPU (the idle symbols are pre-calculated and DMAed into the PIOs, which do the bit banging), and transmission only needs the CPU for framing and encoding, not the timing sensitive / interrupt driven bit-banging stuff.
The ADC example in the README is pretty fun; being able to stream data out to a PC at a high rate over a standard interface is always useful in some niche use case, and I don't think anyone has managed High Speed USB over PIO (yet?) so this is likely to be the fastest way.
Bit-banging isn’t the right term because the toggling isn’t done by the main CPU. The RP series has programmable PIO units which handle the low level timing and line toggling. The CPU communicates with the small program running on the PIO.
Is there some rule that "bit banging" must refer to a primary CPU? I still think it's a good name for "implementing a protocol using instructions that run on a programmable core"; it distinguishes from using dedicated hardware that implements the logic at the gate level / in RTL.
>Bit banging is a term of art that describes a method of digital data transmission as using general-purpose input/output (GPIO) instead of computer hardware that is intended specifically for data communication. [1]
I guess it depends on whether you count the PIO as "general purpose IO" or specific chip for data communication. The ability to run custom programs on them sort of pushes it away from general purpose IO and towards something like a network card that has its own firmware and compute. I think in this case it is fair to say it is debatable.
A network card with its own firmware and compute generally uses a network processor[1], right? A widget that is optimized at the silicon level to put fairly specific pegs into fairly a specific holes?
The RP PIO is not a network processor, and doesn't have that kind of optimization. It is a blank slate that is devoid of intended purpose. It can be used to accomplish lots of different and very arbitrary things.
They seem like very different things to me.
Bit banging is software emulation of a communication protocol or digital waveform (PWM, etc). Using the 'bit-bang' label applies when software was written to implement the waveform. If its using a cpu, or co-processor, is irrelevant IMO because in either case instruction are still being executed to generate the waveform.
As others have already mentioned, the bit banging part is mostly handled by the PIO, so you mostly just spend CPU cycles on 4b5b encoding and scrambling. The more immediate practical problem though is that this is transmit only, no receive.
Combined with RMII ethernet phys only costing around 30 cents even at single quantities definitely makes it just a fun project, though definitely an impressive one at that.
Yeah the first thing that came to mind when I started reading the readme file was "that's not bit-banging -- this is the whole point of PIO."
What other MCU ICs have been demonstrated to use on-die PIO to "not" bit-bang 100BASE-TX Ethernet?
I think a more prudent question is "why not use a microcontroller that has the interfaces you need?"
STM32s with Ethernet are cheap and available, I don't see the point in gymnastics like this
Obviously they are testing the limits, I think most people understand that just because they prove something is possible they aren't saying it's a normal approach.
Even then, pi pico are dirt cheap and have all sorts of features. Reading from i2c or sensors then putting it out over ethernet could be very useful.
The pico has programs that run independently to set the pins, so actually it does leave a lot of CPU cycles.